1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a semiconductor integrated circuit comprising a circuit generating a step-up voltage.
2. Description of the Background Art
A DRAM (dynamic random access memory) employs a step-up voltage VPP having a higher level than an external power supply voltage EXTVCC for driving a word line and/or for an output circuit.
As shown in FIG. 14, a conventional VPP generation circuit generating such a step-up voltage VPP includes a sensing part 90 sensing the level of the step-up voltage VPP, a ring oscillator 95 and a pumping circuit 96.
When the step-up voltage VPP falls below a prescribed reference voltage level, the sensing part 90 senses this and generates an enable signal VPPOSCE enabling the ring oscillator 95.
As shown in FIG. 15, the ring oscillator 95 is formed by a NAND circuit 97 and a plurality of serially connected inverters 98#1 to 98#6. The NAND circuit 97 receives the enable signal VPPOSCE and an output of the inverter 98#6. When the ring oscillator 95 operates, the inverter 98#6 outputs a pulse waveform (pulse signal .phi.) of a constant cycle.
Referring again to FIG. 14, the pumping circuit 96 performs pumping on the basis of the pulse signal .phi. generated from the ring oscillator 95. Thus, charges are supplied to a VPP node for supplying the step-up voltage VPP. Consequently, the step-up voltage VPP corresponding to a prescribed reference voltage VREFD is obtained.
The sensing part 90 includes a sensing circuit 91 operating in a standby state and a sensing circuit 92 operating when an act command ACT is issued (in operation, i.e., when an external row address strobe signal/RAS is low).
As shown in FIG. 16, the sensing circuit 91 includes a comparator 74 provided between the external power supply voltage EXTVCC and a node N1, a constant current source 75 provided between the node N1 and a ground voltage GND and an inverter 76.
The comparator 74 is formed by transistors 70 and 71, a transistor 72 receiving the voltage VPPn obtained by dividing the step-up voltage VPP in its gate electrode and a transistor 73 receiving the reference voltage VREFD in its gate electrode. The inverter 76 inverts a signal on a node N2 between the transistors 71 and 73 and outputs the enable signal VPPOSCE.
As shown in FIG. 17, the sensing circuit 92 is formed by a comparator 74, a constant current source 79, a transistor 80 provided between a node N1 and the constant current source 79 for receiving the act command ACT in its gate electrode and an inverter 76.
As a current flowing to the comparator controlled by the constant current source is increased, the response speed (the time required for the signal VPPOSCE to go high after the step-up voltage VPP falls below the reference voltage VREFD) of the sensing circuit is increased.
In order to improve the response when receiving the act command, therefore, the constant current source 79 feeding a large current (about 10 .mu.A) is employed for the sensing circuit 92. On the other hand, the constant current source 75 feeding a small current (about 2 .mu.A) is employed for the standby sensing circuit 91 for reducing power consumption.
As shown in FIG. 18, a conventional VREFD generation circuit 850 generating the reference voltage VREFD includes a constant current source 84, a resistive element 85 and a PMOS transistor 86 with the ground voltage GND in its gate electrode.
Assuming that the array voltage VDDA which is employed for writing high-level information in a memory cell, is 2.5 V, for example, the step-up voltage VPP must be set to about (VDDA+2.vertline.Vtn.vertline.)=4.5 V, where Vtn represents the threshold voltage of a memory cell transistor.
The constant current source 84, the resistive element 85 and the transistor 86 are connected between the external power supply voltage EXTVCC and the ground voltage GND. A node N4 between the constant current source 84 and the resistive element 85 outputs the reference voltage VREFD. Assuming that I represents the current of the constant current source 84, R represents the resistance value of the resistive element 85 and Vtp represents the threshold voltage of the transistor 86, the reference voltage VREFD is expressed as follows: EQU VREFD=R.times.I+.vertline.Vtp.vertline. (1)
Assuming that the step-up voltage VPP is 4.5 V, the voltage to be sensed is (1/2.times.VPP) and the absolute value .vertline.Vtp.vertline. is 0.8 V, however, the following equation (2) must be satisfied from the equation (1): EQU (R.times.I)=1.45V (2)
In order to form the VREFD generation circuit 850 according to the equation (2), a resistive element having a high resistance value is necessary. Therefore, the resistive element must be formed by a transistor having a large gate length, disadvantageously leading to a large layout area. When increasing the absolute value .vertline.Vtp.vertline. of the threshold voltage in order to solve this problem, the reference voltage VREFD may conceivably be varied with the temperature due to high temperature dependency of the absolute value .vertline.Vtp.vertline..
Further, the reference voltage VREFD output from the VREFD generation circuit 850 is independent of a voltage related to a memory cell array, as shown in the equation (1). Therefore, when the array voltage is increased (particularly by temperature dependency in a test mode or a general operation mode), for example, the difference (VPP-VDDA) is reduced. Thus, charges written in the memory cell are disadvantageously reduced.